![]() Resulting in the creating a path for the flow of current. When the input is logic Low, the PMOS will switch on. As a result, the output will connect with GND, which is logic low. When the input is logic high, the PMOS will switch off & there will be no flow of current because of the breaking of the conductive path. NOTE: PMOS switches on when its gate input is logic Low & it switches off when gate input is logic High. The output is taken between the resistor R & the drain of the NMOS. Input is directly applied to its gate, it does not need input resistor because it operates on input voltage rather than the input current. The Source of NMOS is connected to ground. This NOT gate design using NMOS shows that its drain is connected to a resistor R, which is connected to supply voltage Vdd. The schematic design of NOT gate using NMOS transistor is given below: on the contrary, BJT operates on input current. Mosfets are more economical because of their small sizes & low power consumption. Mosfets such as NMOS, PMOS & CMOS are used in these designs. MOS logic uses Mosfets as the switching devices to implement any logic function. This voltage across resistor R2 is taken as the output, which is logic High. Thus the path for the flow of current will complete & there will be voltage developed across resistor R2. When the input is logic Low, the PNP transistor will switch on because its base input is Low. The output becomes connected to the ground, which is logic low as output. As a result, there will be no current flow because of the breaking of the current flow path. When the input is logic High, the PNP transistor will switch off because its base input is logic High. Note: PNP transistor activates when the input logic is Low and it switches off when the input logic is High. We will discuss this design for both cases of input logic. The output O is taken across the resistor R2 & input is applied to the base of the transistor through resistor R1. In this design, the collector is connected with Vcc of 5v & the emitter is connected to the resistor R2 which is grounded. The schematic design of NOT gate using PNP transistor is given below: This path results in the output as logic Low. True or 1, the NPN transistor will switch on & a conductive path from the output to ground is created. In this case, the input logic is High 5v i.e. So a conductive path will be established between Vcc and output, which makes the output logic High. As a result, there is no current flow through the transistor. False or 0, the NPN transistor will switch off because there is no base current. So it switches on when the input logic is High or True & it switches off when the input logic is Low. Note: NPN transistor switches on when there is base current. We will discuss this schematic for both cases of input logic Input True logic is 5v and False logic is 0v. The supply voltage Vcc = 5v is applied to the circuit. The input line is connected to the base of the transistor through a resistor R1. The output is taken from the collector terminal of NPN. The emitter of NPN is connected directly to the GND. In this schematic design, the collector of NPN is connected with resistor R2, which is connected with Vcc. The schematic design of NOT gate using NPN transistors is: We will discuss the schematic designs using both of them separately in this article. Bi-polar junction transistors ( BJT) are mainly of two types i.e. RTL ( Resistor-Transistor Logic) logic uses resistors and transistors to implement any logic function. So we will discuss schematic designs using different transistors. However, Transistor can invert any signal. NOT gate cannot be designed using diodes, because diodes do not have inversion property and they cannot invert an input signal. The expression for NOT gate uses the symbol ‘ !‘ or ‘ ~‘ as shown in the expression below: And when the input is ‘ 0‘ or False, its output is ‘ 1‘ or True. It shows when the input is ‘ 1‘ or True, its output in ‘ 0‘ or False. The truth table of NOT gate is given below: Input ![]() ![]() ![]() The truth table is a logic table containing the input combinations and their corresponding outputs.Īssume a NOT gate with the input I & output O. The International Electrotechnical Commission symbol:ĭeutsches Institut für Normung symbol for NOT gate, which is used in Germany: The American National standard Institute symbol, it is most commonly used: There are three different symbols used for NOT gate: ANSI NOT gate is a single input single output gate. It implements the logical inversion function. It inverts its input logic into the output. A Digital logic gate which produces logic True when its input is False & generates logic False when its input is True is known as NOT gate or oftenly known as Inverter.īasically, NOT gate is an Inverter.
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